Microsoft's hardware teams incubate advanced technologies and build deep partnerships with internal research, product planning, business, and marketing teams. Microsoft ships tens of millions of hardware products every year, including the Xbox, Surface devices, HoloLens, accessories, and much more. Our opportunities represent a variety of disciplines including, but not limited to, design, verification, performance modeling, and DevOps supporting the development of custom silicon! We are looking for the best and brightest to join us in designing for the future!
As a Principal Engineer, DFT in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our projects. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. In this high impact & highly visible role on the team, you will be responsible for:
The design, implementation and testing of computer hardware products that add strategic value to the company
Specifically, design and develop scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT features on the ATE.
Improve the design, development, and overall quality of the hardware products and development processes. Work on memory BIST design optimization to make sure design is time, power, and area efficient. Collaborate on a regular basis with memory unit owners for DFT architecture and flow development.
Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects. Develop ATE test patterns and algorithms to cover various memory and scan fault models. Work on infrastructure and test flow development for unit level and full chip verification.
Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion. Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project.
Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. Justify and show ROI for BIST and logic redundancy. Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement.
Required Qualifications:
10+ years demonstrated experience in DFT
Excellent debug skills for RTL and gate level simulations
Experience in DFT scan insertion and or Custom Memory BIST design and verification.
Ability to work independently and in a team setting and be able to research innovative solutions for challenging business/technical problems
Solid technical aptitude and problem solving skills, take initiative, and must be result driven strong debugging skills
Strong plus if familiar with Tessent DFT tools from Mentor Siemens.
Well-versed in scan insertion, ATPG, MBIST, JTAG, IO BIST, Scan Compression, and at-speed testing
Experience with industry standard simulation, ATPG and MBIST tools, particularly Mentor
Knowledge of defect types, fault models, silicon bring-up, debug and validation of DFT features on ATE
Experience with 3rd party HSIO DFT and verification of SERDES is a plus
Good communication and analytical skills
Education Qualification:
Master or Bachelor degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent with related engineering experience is required.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the .
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
As a Principal Engineer, DFT in the Silicon Engineering and Solutions team, you will drive DFT solutions for the product and be at the center of chip design and enabling effort all the way from defining architecture, helping with implementation, ensuring verification coverage and finally with silicon bring-up and validation, for our projects. This will involve numerous projects within Microsoft developing custom silicon for a diverse set of systems. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. In this high impact & highly visible role on the team, you will be responsible for:
The design, implementation and testing of computer hardware products that add strategic value to the company
Specifically, design and develop scan insertion and memory BIST (built in self test) insertion, and test the silicon, debug and validate the DFT features on the ATE.
Improve the design, development, and overall quality of the hardware products and development processes. Work on memory BIST design optimization to make sure design is time, power, and area efficient. Collaborate on a regular basis with memory unit owners for DFT architecture and flow development.
Develop methodology and flows for verification and debugging as well as anticipate and avoid blocking issues on projects. Develop ATE test patterns and algorithms to cover various memory and scan fault models. Work on infrastructure and test flow development for unit level and full chip verification.
Proactively identify new tools, technologies, and methods to do the job, and understand customer issues for DFT and BIST insertion. Analyze and compare different tools and methods and compare parameters such as area overhead, timing to optimize the DFT solution for the project.
Evaluate cost of DFT in terms of die are and test time, cost of memory diagnostics, and benefit of yield recovery for logic and memory redundancy. Justify and show ROI for BIST and logic redundancy. Measure repair rates of each chip and identify outlier memory designs that perhaps need circuit work or manufacturing improvement.
Required Qualifications:
10+ years demonstrated experience in DFT
Excellent debug skills for RTL and gate level simulations
Experience in DFT scan insertion and or Custom Memory BIST design and verification.
Ability to work independently and in a team setting and be able to research innovative solutions for challenging business/technical problems
Solid technical aptitude and problem solving skills, take initiative, and must be result driven strong debugging skills
Strong plus if familiar with Tessent DFT tools from Mentor Siemens.
Well-versed in scan insertion, ATPG, MBIST, JTAG, IO BIST, Scan Compression, and at-speed testing
Experience with industry standard simulation, ATPG and MBIST tools, particularly Mentor
Knowledge of defect types, fault models, silicon bring-up, debug and validation of DFT features on ATE
Experience with 3rd party HSIO DFT and verification of SERDES is a plus
Good communication and analytical skills
Education Qualification:
Master or Bachelor degree in Electrical Engineering, Computer Engineering, or Computer Science or equivalent with related engineering experience is required.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the .
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.